Spectral methods
Mapping of spectral methods (FFT, DCT, etc.) to DRRA2 platform. Possibility of RTL development as well.
Scan chains are crucial for the testability of sequential circuits. Scan chain compression techniques aim to reduce the amount of test data, time, and power required for testing high-performance VLSI circuits while maintaining or improving fault coverage. As VLSI designs become more complex, the test data volume grows, leading to longer test times and higher costs. Scan chain compression addresses these issues by compressing test patterns and efficiently decompressing them on-chip. At KTH, we have developed a novel Silago platform. You will explore different compression techniques of scan chains, apply them to our Silago framework, and analyze which is the best suitable for the Silago-based tiled architecture.
Supervisor and Examiner
- Supervisor: Maah Paara mapaar@kth.se
- Examiner: Ahmed Hemani hemani@kth.se
Tasks
- Study and understand the Scan chain compression techniques.
- Study and understand the current Silago framework.
- Apply these techniques to Silago.
- Analyze the best suitable technique for the Silago-based framework.
Required Skills
- TCL programming.
- Computer architecture.
- Knowledge of Design for Testability.
- Logic synthesis using EDA tools, i.e., Genus Cadence.