Instruction level simulator
Developing multi-threaded instruction-level simulation framework for CGRA platform
Motivation
In the process of designing algorithms and mapping them to custom hardware, we rely on an instruction-level simulator to quickly verify the correctness of the algorithm design. The instruction-level simulator is essential because it’s much faster than an RTL simulator and can quickly provide feedback, thus reducing the iteration waiting time of the development process. At KTH, we have developed a novel CGRA platform called DRRA that can greatly improve the efficiency of streaming applications. However, the current instruction-level simulator is single-threaded and outdated. In this degree project, you will upgrade the old DRRA simulator using a thread-friendly event-driven simulation framework proposed in [12].
Supervisor and Examiner
- Supervisor: Yu Yang yuyang2@kth.se
- Examiner: Ahmed Hemani hemani@kth.se
Tasks
- Study and understand the DAM simulation framework.
- Study and understand the current DRRA simulation framework.
- Create a DAM-based simulator for DRRA.
- Maintain the extension interface to incorporate new modules.
Required Skills
- Software development and management.
- Rust and Python programming language.
- Programming with assembly language.
- Operating systems and multi-threading.
- Computer architecture.
References
- N. Zhang et al., “The Dataflow Abstract Machine Simulator Framework”, 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024, pp. 532-547, doi: 10.1109/ISCA59077.2024.00046.
- N. Zhang et al., DAM: The Dataflow Abstract Machine Simulator Framework, https://github.com/stanford-ppl/DAM-RS.