publications

2024

1. Exploration of Custom Floating-Point Formats: A Systematic Approach

   Saba Yousefzadeh, Yu Yang, Astile Peter, and 2 more authors

   In 2024 27th Euromicro Conference on Digital System Design (DSD), 2024

2023

1. Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms

   Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, and 2 more authors

   In 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2023
2. Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks

   Jiawei Xu, Yi Zheng, Chenxu Sheng, and 7 more authors

   In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023

2022

1. Reducing the Configuration Overhead of the Distributed Two-level Control System

   Yu Yang, Dimitrios Stathis, and Ahmed Hemani

   In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022

2021

1. 

   Synthesis of predictable global NoC by abutment in synchoros VLSI design

   Jordi Altayó González, Dimitrios Stathis, and Ahmed Hemani

   In Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip, Virtual Event, 2021

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   Synchoros VLSI design style has been proposed as an alternative to the standard cell-based design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, but their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA’s static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives the same results as the commercial EDA tools.

2. Clock Tree Generation by Abutment in Synchoros VLSI Design

   Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, and 1 more author

   In 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021
3. Scheduling Persistent and Fully Cooperative Instructions

   Yu Yang, Ahmed Hemani, and Kolin Paul

   In 2021 24th Euromicro Conference on Digital System Design (DSD), 2021

2020

1. 

   NACU: A Non-Linear Arithmetic Unit for Neural Networks

   Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, and 1 more author

   In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020

2002

1. 

   A network on chip architecture and design methodology

   S. Kumar, A. Jantsch, J.-P. Soininen, and 5 more authors

   In Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, 2002

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1999

1. 

   Lowering power consumption in clock by using globally asynchronous locally synchronous design style

   A. Hemani, T. Meincke, S. Kumar, and 6 more authors

   In Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, New Orleans, Louisiana, USA, 1999

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